(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to improve the etch stop when etching copper surfaces.
(2) Description of the Prior Art
The creation of semiconductor devices requires the deposition and patterning of numerous layers of semiconductor material, which are then patterned and etched to form device features of required dimensions and electrical performance characteristics. After the semiconductor devices essentially have been created, device elements may have to be interconnected in order to create functional entities. As interconnect materials are typically used metallic materials comprising for instance aluminum, tungsten, titanium, copper, polysilicon, polycide or alloys of these metals. Interconnects are formed by first depositing a layer of metallic material and then patterning and etching the layer of metallic material to form the desired interconnect pattern. Layers of wiring material are typically about 1,000 to 10,000 Angstrom thick, more preferably about 4,000 Angstrom. Wiring that serves as interconnect lines is typically about 1,000 and 8,000 Angstrom wide, more preferably about 5,000 Angstrom wide. In addition to forming interconnect traces, contact plugs or vias also form an integral part of an interconnect network. Plugs can be formed using a conducting or metallic substance such as copper, tungsten, wolfram, titanium nitride, molybdenum, silicide and polysilicon, tantalum or a silicide (including, for example, TiSix, WSix, NiSix, MoSix, TaSix, PdSix, CoSix and others).
As part of the creation of metal interconnects, layers that serve purposes other than forming a conductive interface between points are frequently applied for reasons of device performance requirements and reliability. Such layers include for instance the well known application of a layer of seed material, to enhance adhesion between overlying layers of which the upper layer is a conductive layer, or barrier layers, to prevent diffusion of metallic substance into surrounding dielectrics.
A number of methods are widely used for the creation of a layer of conductive material such as methods of sputter, electro or electroless metal deposition and methods of CVD. For instance, EDS bath processing can be applied for the creation of a layer of copper at a temperature between about 25 and 50 degrees, the source of deposition being the dilution of H2SO4, CuSO4 and HCl with a deposition flow rate of between about 15K and 20 K sccm, a deposition time of between about 1 and 10 minutes, a voltage being applied to the anode of the EDS bath of between about 0.1 and 2 volts and a voltage being applied to the cathode of between about 0.1 and 2 volts. The EDS process is particularly suited for the creation of copper metal plugs, since the copper plug is created in a well-controlled manner due to the fact that EDS Cu deposits copper only on places that have a copper seed layer.
Interconnect contacts or vias are typically created by first depositing a layer of dielectric over a metallic layer, preferable comprising copper, etching openings through the layer of dielectric in the locations where the interconnect contacts or vias are to be located and filling the created openings with a conductive substance, electrically contacting the underlying layer of copper. The etch of the layer of dielectric requires a layer of etch stop material which effectively stops the etch through the layer of dielectric at the surface of the underlying layer of copper. The layer of etch stop material must have good adhesion to the underlying copper surface in order to prevent problems of etch or adhesion of the overlying layer of dielectric resulting in problems of device reliability. The invention provides such a layer by providing an adhesion promotion layer for the adhesion of an etch stop layer that has been deposited over a copper surface. The layer of adhesion promotion material of the invention assures strong adhesion to the underlying copper surface and to the overlying etch stop layer.
U.S. Pat. No. 6,136,680 (Lai et al.) shows a SiC layer on copper 30, see FIG. 6.
U.S. Pat. No. 6,100,587 (Merchant et al.) shows SiC barrier layers in a copper interconnect process.
U.S. Pat. No. 5,946,601 (Wong et al.) reveals a carbon-containing barrier layer.